(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method of preventing auto-doping from the top polysilicon layer and the wafer backside in the manufacture of integrated circuits.
(2) Description of the Prior Art
Threshold voltage (V.sub.t) is one of the most critical parameters in a CMOS transistor. Maintaining a uniform V.sub.t is critical to proper device performance. The deliberate implantation of dopant species into active areas in the silicon substrate to adjust the transistor V.sub.t is standard practice in the manufacture of semiconductors. However, these active areas can also be unintentionally doped, in a process called auto-doping.
Auto-doping of an integrated circuit can occur whenever both highly doped regions and non-doped or lesser-doped regions are exposed during a high temperature processing step. Dopant from the highly doped regions will tend to out-gas into the thermal chamber and then re-diffuse into the non-doped or lesser-doped regions on the substrate. Of particular concern in the present invention is the problem of auto-doping of the active areas of planned CMOS transistors due to the movement of ions from heavily doped polysilicon structures to these active areas.
FIG. 1 illustrates the auto-doping problem in the prior art. A capacitor 24 has been fabricated overlying a field oxide region 12 on a semiconductor substrate 10 that is doped n-type. The capacitor comprises a polysilicon bottom electrode 14, a tungsten silicide (Wsi.sub.x) layer 16, a dielectric layer 18, and a highly doped top polysilicon electrode 20. Also shown is the gate structure 22 for a partially completed PMOS transistor.
During a thermal cycle event, such as the anneal of the tungsten silicide layer to reduce its resistivity, phosphorous dopant 26 from the top capacitor electrode 20 out-diffuses into the thermal chamber atmosphere. The phosphorous dopant 26 then diffuses into the substrate where the surfaces of the source and drain regions 28 of the planned PMOS transistor are exposed. The phosphorous will then laterally and vertically diffuse and increase the n-type dopant concentration near or under the edge of the channel region. Because of the higher concentration of n-type dopant near the channel region, a higher gate voltage will have to be applied to invert the channel region in order to form a conductive channel from source to drain. This is the negative consequence of auto-doping.
The auto-doping problem is made even worse if the upper polysilicon layer is deposited using a diffusion deposition technique where the phosphorous is insitu doped during the polysilicon deposition. In this case, heavily doped polysilicon will cover the backside of the semiconductor wafer. In a subsequent thermal cycle event, such as the aforementioned tungsten silicide anneal, this polysilicon acts a major source for phosphorous out-gassing and, therefore, potential auto-doping effects.
Several prior art approaches attempt to reduce various auto-doping problems. U.S. Pat. No. 4,753,895 to Mayer et al teaches a method to reduce auto-doping of aluminum from a sapphire (Al.sub.2 O.sub.3) dielectric into semiconductor islands during an annealing step in a semiconductor on sapphire process. Ion implantation depths specific to p-channel and n-channel devices are disclosed. U.S. Pat. No. 5,492,868 to Lin et al teaches a method of forming an oxide capping layer over the entire surface before BPSG reflow to prevent auto-doping of source, drain, and gate contact areas. U.S. Pat. No. 5,024,962 to Murray et al teaches a sealing oxide layer formed over the substrate, prior to the deposition of the polysilicon gate layer, to prevent auto-doping from source, drain, and backside regions into exposed channel regions. U.S. Pat. No. 5,648,282 to Yoneda teaches a method to thermally grow a 5 nanometer layer of oxide overlying the surface of the wafer, including overlying any doped polysilicon on both the front and backside of the wafer, to prevent auto-doping during subsequent thermal processing. This layer of oxide is grown after the definition of the polysilicon gates and the implantation of the lightly doped drains. U.S. Pat. No. 4,894,349 to Saito et al teaches an auto-doping prevention technique for epitaxial layers where a first-stage epitaxial layer is grown undoped and a second-stage epitaxial layer is grown doped as desired. U.S. Pat. No. 5,070,382 to Cambou et al teaches an auto-doping prevention for epitaxial layers where a second epitaxial layer is grown with higher resistivity to reduce auto-doping to a third epitaxial layer. Finally, co-pending U.S. patent application Ser. No. 09/058,127 to C.F. Chen et al filed on Apr. 10, 1998, discloses a dual layer polysilicon deposition where an undoped polysilicon is deposited over a doped polysilicon to prevent auto-doping.